105
Therefore, in this section, we examine the performance impact of NIC as a func 
tion of PCI bandwidth. We also evaluate the projected configuration where the NIC
is attached to the memory bus directly (memory attached). The UCB and CSE traces
are chosen for the experiment with the exclusive and inclusive NIC caching, respec 
tively, since they show significant performance improvement with the corresponding NIC
caching schemes. The results in Figures 5.12 and 5.13 are obtained from experiments
conducted in an 8 node cluster configuration. Figure 5.12 shows the throughput with
the exclusive NIC caching scheme. Since the UCB trace incurs the minimum PCI traffic
and the performance gain from the exclusive caching scheme comes from the extended
caching space, the reduction of the PCI overhead does not affect the performance of the
original server or the NIC caching scheme significantly. Thus, with workloads which have
similar characteristics, the exclusive NIC caching scheme can yield similar performance
benefit regardless the PCI bandwidth.
In contrast, Figure 5.13 shows that the inclusive caching scheme significantly im 
proves the throughput and latency even under the high performance PCI (PCI X and
x1 PCI Express) and memory attached I/O. In the original configuration, jobs which
need intra cluster communication, disk access and communication through the Ether 
net, compete for the PCI bus bandwidth. By attaching the NICs to the memory bus,
the performance of the original Web server improves performance significantly. On the
other hand, the proposed caching scheme already significantly alleviates the PCI bus
contention. Thus, the benefit gained from switching from the PCI bus to the memory
bus, while visible, is not that significant. The throughput of the inclusive caching scheme
with PCI X, PCI Express and memory attached I/O increases by 2%, 3% and 9%. On












  

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